ST STM32WL55JC User Manual

RM0453 Rev 2 95/1454
RM0453 Global security controller (GTZC)
96
3.6.3 GTZC TZIC interrupt status clear register 1 (GTZC_TZIC_ICR1)
Address offset: 0x020
Reset value: 0x0000 0000
This register can only be access by a secure privileged access for read and write. A non
secure or unprivileged access is ignored and return zero data and an illegal access event is
generated.
Note: When the system is non-secure (ESE = 0), this register cannot be written and reads zero.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. PKACF
SRAM2
CF
SRAM1
CF
FLASH
CF
DMAM
UX1CF
DMA2
CF
DMA1
CF
FLASHI
FCF
PWR
CF
SUBG
HZSPI
CF
RNG
CF
AESCF
TZSC
CF
TZIC
CF
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PKACF: Illegal access event interrupt status flag clear bit for PKA
0: No action
1: Clear status flag
Bit 12 SRAM2CF: Illegal access event interrupt status flag clear bit for SRAM2
0: No action
1: Clear status flag
Bit 11 SRAM1CF: Illegal access event interrupt status flag clear bit for SRAM1
0: No action
1: Clear status flag
Bit 10 FLASHCF: Illegal access event interrupt status flag clear bit for Flash memory
0: No action
1: Clear status flag
Bit 9 DMAMUX1CF: Illegal access event interrupt status flag clear bit for DMAMUX1
0: No action
1: Clear status flag
Bit 8 DMA2CF: Illegal access event interrupt status flag clear bit for DMA2
0: No action
1: Clear status flag
Bit 7 DMA1CF: Illegal access event interrupt status flag clear bit for DMA1
0: No action
1: Clear status flag
Bit 6 FLASHIFCF: Illegal access event interrupt status flag clear bit for Flash interface
0: No action
1: Clear status flag
Bit 5 PWRCF: Illegal access event interrupt status flag clear bit for PWR
0: No action
1: Clear status flag

ST STM32WL55JC Specifications

General

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English