ST STM32WL55JC User Manual

Global security controller (GTZC) RM0453
96/1454 RM0453 Rev 2
3.6.4 GTZC TZIC register map
Refer to Section 2.6 for the register boundary addresses.
Bit 4 SUBGHZSPICF: Illegal access event interrupt status flag clear bit for sub-GHz SPI
0: No action
1: Clear status flag
Bit 3 RNGCF: Illegal access event interrupt status flag clear bit for RNG
0: No action
1: Clear status flag
Bit 2 AESCF: Illegal access event interrupt status flag clear bit for AES
0: No action
1: Clear status flag
Bit 1 TZSCCF: Illegal access event interrupt status flag clear bit for GTZC TZSC
0: No action
1: Clear status flag
Bit 0 TZICCF: Illegal access event interrupt status flag clear bit for GTZC TZIC
0: No action
1: Clear status flag
Table 10. TZIC register map and reset values
Offset
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
11
10
9 8 7 6 5 4 3 2 1 0
0x000
GTZC_TZIC_IER1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PKAIE
SRAM2IE SRAM1IE
F:LASHIE
DMAMUX1IE
DMA2IE DMA1IE
FLASHIFIE
PWRIE
SUBGHZSPIIE
RNGIE
AESIE
TZSCIE
TZICIE
Reset value xxxxxxxxxxxxxx
0x004
to
0x00C
Reserved Reserved
0x010
GTZC_TZIC_MISR1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PKAMF
SRAM2MF SRAM1MF
FLASHMF
DMAMUX1MF
DMA2MF DMA1MF
FLASHIFMF
PWRMF
SUBGHZSPIMF
RNGMF
AESMF
TZSCMF
TZICMF
Reset value 00000000000000
0x014
to
0x01C
Reserved Reserved
0x020
GTZC_TZIC_ICR1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PKACF
SRAM2CF SRAM1CF
FLASHCF
DMAMUX1CF
DMA2CF DMA1CF
FLASHIFCF
PWRCF
SUBGHZSPICF
RNGCF
AESCF
TZSCCF
TZICCF
Reset value 00000000000000

ST STM32WL55JC Specifications

General

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English