ST STM32WL55JC

Advanced-control timer (TIM1) RM0453
736/1454 RM0453 Rev 2
Figure 143. Counter timing diagram, internal clock divided by 2
Figure 144. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
MS31190V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0003
0002
0001
0000
0001
0002
0003
0034 0035
MS31191V1
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
CNT_EN
Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow
0036 0035