Real-time clock (RTC) RM0453
1012/1454 RM0453 Rev 2
32.6.3 RTC sub second register (RTC_SSR)
Address offset: 0x08
Backup domain reset value: 0x0000 0000
System reset value: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
32.6.4 RTC initialization control and status register (RTC_ICSR)
This register is write protected. The write access procedure is described in RTC register
write protection on page 999.
Address offset: 0x0C
Backup domain reset value: 0x0000 0007
System reset: not affected except INIT, INITF, and RSF bits which are cleared to 0
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SS[31:16]
rrrrrrrrrrrrrrrr
1514131211109876543210
SS[15:0]
rrrrrrrrrrrrrrrr
Bits 31:0 SS[31:0]: Synchronous binary counter
SS[31:16]: Synchronous binary counter MSB values
When Binary or Mixed mode is selected (BIN = 01 or 10 or 11):
SS[31:16] are the 16 MSB of the SS[31:0] free-running down-counter.
When BCD mode is selected (BIN=00):
SS[31:16] are forced by hardware to 0x0000.
SS[15:0]: Sub second value/Synchronous binary counter LSB values
When Binary mode is selected (BIN = 01 or 10 or 11):
SS[15:0] are the 16 LSB of the SS[31:0] free-running down-counter.
When BCD mode is selected (BIN=00):
SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given
by the formula below:
Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1)
SS can be larger than PREDIV_S only after a shift operation. In that case, the correct
time/date is one second less than as indicated by RTC_TR/RTC_DR.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RECAL
PF
r
1514131211109876543210
Res. Res. Res. BCDU[2:0] BIN[1:0] INIT INITF RSF INITS SHPF
WUTW
F
Res. Res.
rw rw rw rw rw rw r rc_w0 r r r
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