ST STM32WL55JC User Manual

RM0453 Rev 2 643/1454
RM0453 True random number generator (RNG)
647
22.6.3 Data collection
In order to run statistical tests it is required to collect samples from the entropy source at raw
data level as well as at the output of the entropy source. For details on data collection and
the running of statistical test suites refer to “STM32 microcontrollers random number
generation validation using NIST statistical test suite” application note (AN4230) available
from www.st.com.
Contact STMicroelectronics if above samples need to be retrieved for your product.
22.7 RNG registers
The RNG is associated with a control register, a data register and a status register.
22.7.1 RNG control register (RNG_CR)
Address offset: 0x000
Reset value: 0x0080 0000
1. When writing this register magic number 0x17590ABC must be written immediately before the indicated value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CONFI
GLOCK
COND
RST
Res. Res. Res. Res. RNG_CONFIG1[5:0] CLKDIV[3:0]
rs rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG_CONFIG2[2:0] NISTC RNG_CONFIG3[3:0] Res. Res. CED Res. IE RNGEN Res. Res.
rw rw rw rw rw rw rw rw rw rw rw
Bit 31 CONFIGLOCK: RNG Config lock
0: Writes to the RNG_CR configuration bits [29:4] are allowed.
1: Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset.
This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset.
Bit 30 CONDRST: Conditioning soft reset
Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new
RNG initialization process, with RNG_SR cleared. Registers RNG_CR and RNG_NSCR are
not changed by CONDRST.
This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other
words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be
written.
When CONDRST is set to 0 by software its value goes to 0 when the reset process is done.
It takes about 2 AHB clock cycles + 2 RNG clock cycles.
Bits 29:26 Reserved, must be kept at reset value.
Bits 25:20 RNG_CONFIG1[5:0]: RNG configuration 1
Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended
value documented in Section 22.6: RNG entropy source validation.
Writing any bit of RNG_CONFIG1 is taken into account only if CONDRST bit is set to 1 in the
same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if
CONFIGLOCK = 1.

ST STM32WL55JC Specifications

General

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English