Comparator (COMP) RM0453
624/1454 RM0453 Rev 2
21.3.3 COMP reset and clocks
The COMP clock provided by the clock controller is synchronous with the APB2 clock.
There is no clock enable control bit provided in the RCC controller. Reset and clock enable
bits are common for COMP and SYSCFG.
Note: Important: The polarity selection logic and the output redirection to the port works
independently from the APB2 clock. This allows the comparator to work even in Stop mode.
21.3.4 Comparator LOCK mechanism
The comparators can be used for safety purposes, such as over-current or thermal
protection. For applications with specific functional safety requirements, the comparator
configuration can be protected against undesired alteration that may happen, for example,
at program counter corruption.
For this purpose, the comparator configuration registers can be write-protected (read-only).
Once the programming is completed, the COMPx LOCK bit can be set to 1. This causes the
whole register to become read-only, including the COMPx LOCK bit.
The write protection can only be removed through the MCU reset.
21.3.5 Window comparator
The purpose of the window comparator is to monitor the analog voltage and check that it is
comprised within the specified voltage range defined by lower and upper thresholds.
COMP1 and COMP2 can be utilized to create window comparator. The monitored analog
voltage is connected to the non-inverting (plus) inputs of comparators connected together,
and the upper and lower threshold voltages are connected to the inverting (minus) inputs of
the comparators. The two non-inverting inputs can be connected internally together by
enabling the WINMODE bit to save one I/O for other purposes.
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