RM0453 Rev 2 841/1454
RM0453 General-purpose timer (TIM2)
893
Figure 212. Control circuit in external clock mode 2
26.3.4 Capture/Compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Figure 213. Capture/Compare channel (example: channel 1 input stage)
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
MSv33111V3
34 35 36
f
CK_INT
CNT_EN
ETR
ETRP
ETRF
Counter clock =
CK_CNT =CK_PSC
Counter register
MSv40120V1
0
1
ICPS[1:0]
TI1F_ED
To the slave mode controller
TI1FP1
11
01
CC1S[1:0]
IC1
TI2FP1
TRC
(from slave mode
controller)
10
IC1PS
0
1
TIMx_CCER
CC1P/CC1NP
TIMx_CCMR1
Edge
detector
TI1F_Rising
TI1F_Falling
Filter
downcounter
ICF[3:0]
Divider
/1, /2, /4, /8
TIMx_CCMR1
TIMx_CCER
TI2F_Rising
(from channel 2)
TI2F_Falling
(from channel 2)
TI1F
f
DTS
CC1E
TIMx_CH1
TI1[1..15]
TI1[0]
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