RM0453 Rev 2 101/1454
RM0453 Embedded Flash memory (FLASH)
153
4.3.5 Adaptive real-time memory accelerator (ART Accelerator)
The proprietary adaptive real-time (ART) memory accelerator is optimized for STM32
industry-standard Arm
Cortex-M4 with DSP processors. It balances the inherent
performance advantage of the Cortex-M4 with DSP over Flash memory technologies, which
normally require the processor to wait for the Flash memory at higher operating frequencies.
To release the processor full performance, the accelerator implements an instruction
prefetch queue and branch cache that increases program execution speed from the 64-bit
Flash memory. Based on CoreMark
®
benchmark, the performance achieved thanks to the
ART Accelerator is equivalent to 0 wait state program execution from the Flash memory at a
CPU frequency up to 48 MHz.
Instruction prefetch
The CPU1 fetches the instruction over the ICode bus and the literal pool (constant/data)
over the DCode bus. The prefetch block aims at increasing the efficiency of ICode bus
accesses.
The CPU2 fetches the instruction and the literal pool (constant/data) over the S-bus. The
prefetch block aims at increasing the efficiency of S-bus accesses.
Each Flash memory read operation provides 64 bits from either two instructions of 32 bits or
four instructions of 16 bits according to the program launched. This 64-bit current instruction
line is saved in a current buffer. In case of sequential code, at least two CPU cycles are
needed to execute the previous read instruction line. Prefetch on the CPU1 ICode bus or
CPU2 S-bus can be used to read the next sequential instruction line from the Flash memory
while the current instruction line is being requested by the CPU.
Prefetch is enabled by setting PRFTEN in FLASH_ACR for CPU1 or FLASH_C2ACR for
CPU2. This feature is useful if at least one wait state is needed to access the Flash memory.
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