RM0453 Rev 2 963/1454
RM0453 Low-power timer (LPTIM)
973
28.7.3 LPTIM interrupt enable register (LPTIM_IER)
Address offset: 0x008
Reset value: 0x0000 0000
Bit 2 EXTTRIGCF: External trigger valid edge clear flag
Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register
Bit 1 ARRMCF: Autoreload match clear flag
Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register
Bit 0 CMPMCF: Compare match clear flag
Writing 1 to this bit clears the CMP flag in the LPTIM_ISR register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res.
REPOK
IE
UEIE
DOWNI
E
UPIE
ARRO
KIE
CMPO
KIE
EXT
TRIGIE
ARRM
IE
CMPM
IE
rw rw rw rw rw rw rw rw rw
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 REPOKIE: Repetition register update OK interrupt Enable
0: Repetition register update OK interrupt disabled
1: Repetition register update OK interrupt enabled
Bit 7 UEIE: Update event interrupt enable
0: Update event interrupt disabled
1: Update event interrupt enabled
Bit 6 DOWNIE: Direction change to down Interrupt Enable
0: DOWN interrupt disabled
1: DOWN interrupt enabled
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 28.3: LPTIM implementation.
Bit 5 UPIE: Direction change to UP Interrupt Enable
0: UP interrupt disabled
1: UP interrupt enabled
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 28.3: LPTIM implementation.
Bit 4 ARROKIE: Autoreload register update OK Interrupt Enable
0: ARROK interrupt disabled
1: ARROK interrupt enabled
Bit 3 CMPOKIE: Compare register update OK Interrupt Enable
0: CMPOK interrupt disabled
1: CMPOK interrupt enabled
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