ST STM32WL55JC

Advanced-control timer (TIM1) RM0453
732/1454 RM0453 Rev 2
Figure 137. Counter timing diagram, internal clock divided by 1
Figure 138. Counter timing diagram, internal clock divided by 2
36
34
33
32 31
30 2F
04
03
02 01 00
05
MS31184V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
(cnt_udf)
Update interrupt flag
(UIF)
35
MS31185V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0002
0001
0000
0036
0035
0034
0033