ST STM32WL55JC User Manual (English)

To Next Page

To Previous Page

Debug support (DBG) RM0453

1320/1454 RM0453 Rev 2

The two modes are mutually exclusive since they share the same I/O pins.

By default the JTAG-DP is selected after a system or a power-on reset. The five I/O pins are

configured by hardware in debug alternative function mode.

The SWJ-DP incorporates pull-up resistors on JTDI, JTMS/SWDIO and nJTRST, as well as

a pull-down resistor on JTCK/SWCLK.

A debugger can select the SW-DP by transmitting the following serial data sequence on

JTMS/SWDIO:

... (50 or more ones) ..., 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, ... (50 or more ones) ...

JTCK/SWCLK must be cycled for each data bit.

In SW-DP mode, the unused JTAG pins JTDI, JTDO and nJTRST can be used for other

functions.

Note: All SWJ port I/Os can be reconfigured to other functions by software but debugging is no

longer possible.

38.3.8 JTAG debug port

The JTAG debug port (JTAG-DP) implements a TAP state machine (TAPSM) shown in

Figure 384, based on IEEE Std 1149.1-1990. The state machine controls two scan chains,

one associated with an instruction register (IR) and the other one with a number of data

registers (DR).

ST STM32WL55JC User Manual