General-purpose I/Os (GPIO) RM0453
408/1454 RM0453 Rev 2
10.4.11 GPIOx bit reset register (GPIOx_BRR) (x = A to B)
Address offset: Block A: 0x0028
Address offset: Block B: 0x0428
Reset value: 0x0000 0000
10.4.12 GPIOC mode register (GPIOC_MODER)
Address offset: 0x0800
Reset value: 0xFC00 3FFF
Bits 19:16 AFSEL12[3:0]: Port Px12 alternate function selection
Bits 15:12 AFSEL11[3:0]: Port Px11 alternate function selection
Bits 11:8 AFSEL10[3:0]: Port Px10 alternate function selection
Bits 7:4 AFSEL9[3:0]: Port Px9 alternate function selection
Bits 3:0 AFSEL8[3:0]: Port Px8 alternate function selection
These bits are written by software to configure alternate function I/Os
0x0: AF0 selected
0x1: AF1 selected
0x2: AF2 selected
...
0xE: AF14 selected
0xF: AF15 selected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 BR[15:0]: Port Px[15:0] reset output data bit [15:0] in GPIOx_ODR.
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15)
1: Resets the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE15[1:0] MODE14[1:0] MODE13[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw
1514131211109876543210
Res. Res. MODE6[1:0] MODE5[1:0] MODE4[1:0] MODE3[1:0] MODE2[1:0] MODE1[1:0] MODE0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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