RM0453 Rev 2 389/1454
RM0453 Inter-processor communication controller (IPCC)
391
9.4.7 IPCC processor 2 status set clear register (IPCC_C2SCR)
Address offset: 0x018
Reset value: 0x0000 0000
Reading this register always returns 0x0000 0000.
Bits 21:16 CHnFM: Processor 2 transmit channel n free interrupt mask (n = 6 to 1).
Associated with IPCC_C2TOC1SR.CHnF
1: Transmit channel n free interrupt masked.
0: Transmit channel n free interrupt not masked.
Bits 15:6 Reserved, must be kept at reset value.
Bits 5:0 CHnOM: Processor 2 receive channel n occupied interrupt mask (n = 6 to 1).
Associated with IPCC_C1TOC2SR.CHnF
1: Receive channel n occupied interrupt masked.
0: Receive channel n occupied interrupt not masked.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CH6S CH5S CH4S CH3S CH2S CH1S
rw rw rw rw rw rw
15141312111098765 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CH6C CH5C CH4C CH3C CH2C CH1C
rw rw rw rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:16 CHnS: Processor 2 transmit channel n status set (n = 6 to 1).
Associated with IPCC_C2TOC1SR.CHnF
1: Processor 2 transmit channel n status bit set.
0: No action.
Bits 15:6 Reserved, must be kept at reset value.
Bits 5:0 CHnC: Processor 2 receive channel n status clear (n = 6 to 1).
Associated with IPCC_C1TOC2SR.CHnF
1: Processor 2 receive channel n status bit clear.
0: No action.
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