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ST STM32WL55JC User Manual

ST STM32WL55JC
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RM0453 Rev 2 1157/1454
RM0453 Universal synchronous/asynchronous receiver transmitter (USART/UART)
1257
encoded. While receiving data, transmission should be avoided as the data to be
transmitted could be corrupted.
A ‘0‘ is transmitted as a high pulse and a ‘1 is transmitted as a ‘0’. The width of the
pulse is specified as 3/16th of the selected bit period in normal mode (see Figure 324).
The SIR decoder converts the IrDA compliant receive signal into a bit stream for
USART.
The SIR receive logic interprets a high state as a logic one and low pulses as logic
zeros.
The transmit encoder output has the opposite polarity to the decoder input. The SIR
output is in low state when Idle.
The IrDA specification requires the acceptance of pulses greater than 1.41 µs. The
acceptable pulse width is programmable. Glitch detection logic on the receiver end
filters out pulses of width less than 2 PSC periods (PSC is the prescaler value
programmed in the USART_GTPR). Pulses of width less than 1 PSC period are always
rejected, but those of width greater than one and less than two periods may be
accepted or rejected, those greater than two periods are accepted as a pulse. The IrDA
encoder/decoder doesn’t work when PSC = 0.
The receiver can communicate with a low-power transmitter.
In IrDA mode, the stop bits in the USART_CR2 register must be configured to ‘1 stop
bit’.
IrDA low-power mode
Transmitter
In low-power mode, the pulse width is not maintained at 3/16 of the bit period. Instead,
the width of the pulse is 3 times the low-power baud rate which can be a minimum of
1.42 MHz. Generally, this value is 1.8432 MHz (1.42 MHz < PSC < 2.12 MHz). A low-
power mode programmable divisor divides the system clock to achieve this value.
Receiver
Receiving in low-power mode is similar to receiving in normal mode. For glitch
detection the USART should discard pulses of duration shorter than 1/PSC. A valid low
is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud
clock (PSC value in the USART_GTPR).
Note: A pulse of width less than two and greater than one PSC period(s) may or may not be
rejected.
The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and reception (IrDA
is a half duplex protocol).

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ST STM32WL55JC Specifications

General IconGeneral
SeriesSTM32WL
Speed48MHz
Flash Memory256 KB
RAM64 KB
Voltage - Supply (Vcc/Vdd)1.8 V ~ 3.6 V
RF Frequency150MHz ~ 960MHz
Data ConvertersA/D 12x12b; D/A 1x12b
ADC Channels12
DAC Channels1
Sub-GHz RadioYes
Core ProcessorARM Cortex-M4
ConnectivityI2C, SPI, UART
Oscillator TypeInternal
Operating Temperature-40°C ~ 85°C
Communication InterfacesI2C, SPI, USART
Wireless ConnectivityLoRa, Sigfox
Radio Frequency Range150MHz ~ 960MHz
PeripheralsDMA, POR, PWM, WDT

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