ST STM32WL55JC User Manual

Real-time clock (RTC) RM0453
996/1454 RM0453 Rev 2
BCD mode (BIN=00)
A programmable prescaler stage generates a 1 Hz clock which is used to update the
calendar. To minimize power consumption, the prescaler is split into 2 programmable
prescalers (see Figure 273: RTC block diagram):
• A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the
RTC_PRER register.
• A 15-bit synchronous prescaler configured through the PREDIV_S bits of the
RTC_PRER register.
Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
The asynchronous prescaler division factor is set to 128, and the synchronous division
factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency
of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 2
22
.
This corresponds to a maximum input frequency of around 4 MHz.
f
ck_apre
is given by the following formula:
The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it
reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.
f
ck_spre
is given by the following formula:
The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit
wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload
timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous
prescaler (see Section 32.3.8: Periodic auto-wakeup for details).
Binary mode (BIN=01)
The SSR binary down-counter is extended to 32-bit length and is free running. The time and
date calendar BCD registers are not functional.
This down-counter is clocked by ck_apre: the output of the 7-bit asynchronous prescaler
configured through the PREDIV_A bits of the RTC_PRER register.
PREDIV_S value is don’t care.
Mixed mode (BIN=10 or 11)
The SSR binary down-counter is extended to 32-bit length and is free running. The time and
date calendar BCD registers are also available.
This down-counter is clocked by ck_apre: the output of the 7-bit asynchronous prescaler
configured through the PREDIV_A bits of the RTC_PRER register. The bits BCDU[2:0] are
f
CK_APRE
f
RTCCLK
PREDIV_A 1+
---------------------------------------=
f
CK_SPRE
f
RTCCLK
PREDIV_S 1+()PREDIV_A 1+()×
----------------------------------------------------------------------------------------------=

ST STM32WL55JC Specifications

General

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English