ST STM32WL55JC - Figure 240. Counter Timing Diagram, Internal Clock Divided by 1; Figure 241. Counter Timing Diagram, Internal Clock Divided by 2

RM0453 Rev 2 901/1454
RM0453 General-purpose timers (TIM16/TIM17)
944
Figure 244. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
Figure 245. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
FF 36
MS31082V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
00
02
03 04 05
06
0732
33
34 35
3631
01
CEN
Auto-reload preload
register
Write a new value in TIMx_ARR
MS31083V2
F5
36
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
00
02
03 04 05
06
07F1
F2
F3 F4
F5F0
01
CEN
Auto-reload preload
register
Write a new value in TIMx_ARR
Auto-reload shadow
register
F5
36