Inter-processor communication controller (IPCC) RM0453
378/1454 RM0453 Rev 2
9 Inter-processor communication controller (IPCC)
9.1 IPCC introduction
The inter-processor communication controller (IPCC) is used for communicating data
between two processors.
The IPCC block provides a non blocking signaling mechanism to post and retrieve
communication data in an atomic way. It provides the signaling for twelve channels:
• six channels in the direction from processor 1 to processor 2
• six channels in the opposite direction
It is then possible to have two different communication types in each direction.
The IPCC communication data must be located in a common memory, which is not part of
the IPCC block.
9.2 IPCC main features
• Status signaling for the twelve channels
– Channel occupied/free flag, also used as lock
• Two interrupt lines per processor
– One for RX channel occupied (communication data posted by sending processor)
– One for TX channel free (communication data retrieved by receiving processor)
• Interrupt masking per channel
– Channel occupied mask
– Channel free mask
• Two channel operation modes
– Simplex (each channel has its own communication data memory location)
– Half duplex (a single channel associated to a bidirectional communication data
information memory location)
9.3 IPCC functional description
The IPCC communication data is located in a common memory, which is not part of the
IPCC block. The address location of the communication data must be known or located in a
known common area that, as already stated, is not part of the IPCC block.
For each communication, the IPCC block provides a channel status flag CHnF.
• When 0, the channel status flag CHnF indicates that the associated IPCC channel is
free (communication data has been retrieved by the receiving processor), and can be
accessed by the sending processor.
• When 1, the channel status flag CHnF indicates that the associated IPCC channel is
occupied (communication data has been posted by the sending processor) and can be
accessed by the receiving processor.
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