ST STM32WL55JC - Figure 191. Counter Timing Diagram, Internal Clock Divided by 1

RM0453 Rev 2 829/1454
RM0453 General-purpose timer (TIM2)
893
Figure 194. Counter timing diagram, internal clock divided by N
Figure 195. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)
00
1F
20
MS31081V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
FF 36
MS31082V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
00
02
03 04 05
06
0732
33
34 35
3631
01
CEN
Auto-reload preload
register
Write a new value in TIMx_ARR