Reset and clock control (RCC) RM0453
280/1454 RM0453 Rev 2
– LSI clock
– HSE32 clock divided by 32
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE.
• The IWDG clock is always the LSI clock.
The RCC feeds the CPU1 system timer (SysTick) external clock with the AHB clock
(HCLK1) divided by eight. The SysTick can work either with this clock or directly with the
CPU1 clock (HCLK1), configurable in the SysTick control and status register.
FCLK1 acts as CPU1 free-running clock. For more details, refer to the programming manual
STM32 Cortex
®
-M4 MCUs and MPUs programming manual (PM0214).
The RCC feeds the CPU2 system timer (SysTick) external clock with the AHB clock
(HCLK2) divided by eight. The SysTick can work either with this clock or directly with the
CPU2 clock (HCLK2), configurable in the SysTick control and status register.
FCLK2 acts as CPU2 free-running clock.
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