RM0453 Rev 2 683/1454
RM0453 AES hardware accelerator (AES)
695
Note: AES is not disabled after a WRERR error detection and continues processing.
An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details,
refer to Section 23.5: AES interrupts.
The WRERR flag is cleared by setting the ERRC bit of the AES_CR register.
23.5 AES interrupts
Individual maskable interrupt sources generated by the AES peripheral signal the following
events:
• computation completed
• read error
• write error
The individual sources are combined into the common interrupt signal aes_it that connects
to NVIC (nested vectored interrupt controller). Each can individually be enabled/disabled, by
setting/clearing the corresponding enable bit of the AES_CR register, and cleared by setting
the corresponding bit of the AES_CR register.
The status of each can be read from the AES_SR register.
Table 139 gives a summary of the interrupt sources, their event flags and enable bits.
Table 139. AES interrupt requests
Interrupt
acronym
AES
interrupt event Event flag Enable bit
Interrupt clear
method
AES
computation completed flag CCF CCFIE set CCFC
(1)
read error flag RDERR
ERRIE set ERRC
(1)
write error flag WRERR
1. Bit of the AES_CR register.
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