ST STM32WL55JC User Manual

Power control (PWR) RM0453
264/1454 RM0453 Rev 2
6.6.9 PWR port A pull-up control register (PWR_PUCRA)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x020
Reset value: 0x0000 0000
6.6.10 PWR port A pull-down control register (PWR_PDCRA)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x024
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PU[15:0]: Port PA[y] pull-up bit y (y = 0 to 15)
When set, each bit activates the pull-up on PA[y] when both APC bits are set in PWR control
register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3). The pull-up is
not activated if the corresponding PA[y] bit is also set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PD[15:0]: Port PA[y] pull-down (y = 0 to 15)
When set, each bit activates the pull-down on PA[y] when both APC bits are set in PWR
control register 3 (PWR_CR3) and in PWR CPU2 control register 3 (PWR_C2CR3).

ST STM32WL55JC Specifications

General

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English