ST STM32WL55JC User Manual

Power control (PWR) RM0453
222/1454 RM0453 Rev 2
Warning: During t
RSTTEMPO
(temporization at V
DD
startup) or after a PDR
is detected, the power switch between V
BAT
and V
DD
remains
connected to V
BAT
.
During the startup phase, if V
DD
is established in less than
t
RSTTEMPO
(refer to the datasheet for the value of t
RSTTEMPO
)
and V
DD
> V
BAT
+ 0.6 V, a current can be injected into V
BAT
through an internal diode connected between V
DD
and the
power switch (V
BAT
).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect VBAT
externally to V
DD
with a 100 nF external ceramic decoupling capacitor.
When the Backup domain is supplied by V
DD
(analog switch connected to V
DD
), the
following pins are available:
• PC13, PC14 and PC15, that can be used as GPIO pins
• PC13, PC14 and PC15, that can be configured by RTC, TAMP or LSE (refer to
Section 32: Real-time clock (RTC) and Section 33: Tamper and backup registers
(TAMP))
• PA0/TAMP_IN2 and PB3/TAMP_IN3 when they are configured by the TAMP as tamper
pins
Note: Due to the fact that the analog switch can transfer only a limited amount of current (3 mA),
the use of GPIO PC13 to PC15 in output mode is restricted: the speed must be limited to
2
MHz with a maximum load of 30 pF and these I/Os must not be used as current source
(e.g. to drive a LED).
When the Backup domain is supplied by V
BAT
(analog switch connected to V
BAT
because
V
DD
is not present), the following functions are available:
• PC13, PC14 and PC15 can be controlled only by RTC, TAMP or LSE (refer to
Section 32: Real-time clock (RTC) and Section 33: Tamper and backup registers
(TAMP))
• PA0/TAMP_IN2 and PB3/TAMP_IN3, when they are configured by the TAMP as
tamper pins
Backup domain access
After a system reset, the Backup domain (RTC and TAMP backup registers) is protected
against possible unwanted write accesses. The DBP bit must be set in the PWR control
register 1 (PWR_CR1) to enable access to the Backup domain
VBAT battery charging
When V
DD
is present, It is possible to charge the external battery on VBAT through an
internal resistance.
The VBAT charging is done either through a 5 kΩ resistor or through a 1.5 kΩ resistor,
depending on the VBRS bit value in the PWR control register 4 (PWR_CR4).

ST STM32WL55JC Specifications

General

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English