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RM0453 Rev 2 1409/1454

RM0453 Debug support (DBG)

1441

38.11.17 TPIU CoreSight component identity register 0 (TPIU_CIDR0)

Address offset: 0xFF0

Reset value: 0x0000 000D

38.11.18 TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1)

Address offset: 0xFF4

Reset value: 0x0000 0090

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[7:0]

rrrrrrrr

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[7:0]: component ID bits [7:0]

0x0D: Common ID value

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. CLASS[3:0] PREAMBLE[11:8]

rrrrrrrr

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 CLASS[3:0]: component ID bits [15:12] - component class

0x9: CoreSight component

Bits 3:0 PREAMBLE[11:8]: component ID bits [11:8]

0x0: Common ID value

ST STM32WL55JC User Manual

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