Debug support (DBG) RM0453
1434/1454 RM0453 Rev 2
38.14.2 BPU remap register (BPU_REMAPR)
Address offset: 0x004
Reset value: 0x0000 0000
38.14.3 BPU comparator register x (BPU_COMPxR)
Address offset: 0x008 + 0x004 * x, (x = 0 to 7)
Reset value: 0x0000 0000
Bits 31:15 Reserved, must be kept at reset value.
Bits 11:8 NUM_LIT[3:0]: number of literal address comparators supported (read only)
0x0: No literal comparators supported.
Bits
14,13,12,7,6,5,4
NUM_CODE[6:0]: number of instruction address comparators supported - least significant bits
(read only)
0x8: 8 instruction comparators supported
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 KEY: write protect key
A write to BPU_CTRLR register is ignored if this bit is not set to 1.
Bit 0 ENABLE: BPU enable
0: Disabled
1: Enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res.
RMPSPT
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
r
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 RMPSPT: Flash memory patch remap
Indicates whether Flash memory patch remap is supported (read only).
0: Remapping not supported.
Bits 28:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REPLACE[1:0] Res.
COMP[26:14]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP[13:0]
Res.
ENABL
E
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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