ST STM32WL55JC User Manual

RM0453 Rev 2 331/1454
RM0453 Reset and clock control (RCC)
363
7.4.28 RCC APB3 peripheral clock enable in Sleep mode register
(RCC_APB3SMENR)
Address offset: 0x084
Reset value: 0x0000 0001
Access: word, half-word and byte access
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCSMEN: ADC clocks enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: ADC bus clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: ADC bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
Bits 8:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SUBGHZSPISMEN
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPISMEN: Sub-GHz radio SPI clock enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: Sub-GHz radio SPI clock disabled by the clock gating during CPU1 CSleep and CStop
modes
1: Sub-GHz radio SPI clock enabled by the clock gating during CPU1 CSleep mode,
disabled during CPU1 CStop mode

ST STM32WL55JC Specifications

General

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English