ST STM32WL55JC User Manual

RM0453 Rev 2 441/1454
RM0453 System configuration controller (SYSCFG)
444
11.2.14 SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2)
Address offset: 0x10C
Reset value: 0x0000 0000
Bit 5 RCCIM: RCC interrupt mask to CPU2
0: RCC interrupt forwarded to CPU2
1. RCC interrupt to CPU2 masked
Bit 4 Reserved, must be kept at reset value.
Bit 3 RTCWKUPIM: RTCWKUP interrupt mask to CPU2
0: RTCWKUP interrupt forwarded to CPU2
1. RTCWKUP interrupt to CPU2 masked
Bit 2 RTCSSRUIM: RTC SSRU interrupt mask to CPU2
0: RTC SSRU interrupt forwarded to CPU2
1. RTC SSRU interrupt to CPU2 masked
Bit 1 RTCALARMIM: RTCALARM interrupt mask to CPU2
0: RTCALARM interrupt forwarded to CPU2
1. RTCALARM interrupt to CPU2 masked
Bit 0 RTCSTAMPTAMPLSECSSIM: RTCSTAMPTAMPLSECSS interrupt mask to CPU2
0: RTCSTAMPTAMPLSECSS interrupt forwarded to CPU2
1. RTCSTAMPTAMPLSECSS interrupt to CPU2 masked
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PVDIM Res.
PVM3IM
Res. Res.
rw rw
1514131211109876543210
DMAMUX1IM
DMA2CH7IM DMA2CH6IM DMA2CH5IM DMA2CH4IM DMA2CH3IM DMA2CH2IM DMA2CH1IM
Res.
DMA1CH7IM DMA1CH6IM DMA1CH5IM DMA1CH4IM DMA1CH3IM DMA1CH2IM DMA1CH1IM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 PVDIM: PVD interrupt mask to CPU2
0: PVD interrupt forwarded to CPU2
1. PVD interrupt to CPU2 masked
Bit 19 Reserved, must be kept at reset value.
Bit 18 PVM3IM: PVM3 interrupt mask to CPU2
0: PVM3 interrupt forwarded to CPU2
1. PVM3 interrupt to CPU2 masked.
Bits 17:16 Reserved, must be kept at reset value.
Bit 15 DMAMUX1IM: DMAMUX1 interrupt mask to CPU2
0: DMAMUX1 interrupt forwarded to CPU2
1. DMAMUX1 interrupt to CPU2 masked

ST STM32WL55JC Specifications

General

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English