ST STM32WL55JC User Manual

AES hardware accelerator (AES) RM0453
692/1454 RM0453 Rev 2
23.7.13 AES key register 4 (AES_KEYR4)
Address offset: 0x30
Reset value: 0x0000 0000
23.7.14 AES key register 5 (AES_KEYR5)
Address offset: 0x34
Reset value: 0x0000 0000
23.7.15 AES key register 6 (AES_KEYR6)
Address offset: 0x38
Reset value: 0x0000 0000
Bits 31:0 IVI[127:96]: Initialization vector input, bits [127:96]
Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[159:144]
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1514131211109876543210
KEY[143:128]
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Bits 31:0 KEY[159:128]: Cryptographic key, bits [159:128]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[191:176]
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1514131211109876543210
KEY[175:160]
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Bits 31:0 KEY[191:160]: Cryptographic key, bits [191:160]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[223:208]
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1514131211109876543210
KEY[207:192]
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Bits 31:0 KEY[223:192]: Cryptographic key, bits [223:192]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

ST STM32WL55JC Specifications

General

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English