Xilinx SelectIO 7 Series User Manual

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 73
UG471 (v1.10) May 8, 2018
Supported I/O Standards and Terminations
Figure 1-56 shows a sample circuit illustrating a termination technique for differential
HSTL class-II (1.5V or 1.8V) with on-chip split-thevenin termination. In a specific circuit,
all drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not
interchangeable. Only HP I/O banks support the T_DCI standards. The internal
split-termination resistors are only present when the output buffers are 3-stated.
X-Ref Target - Figure 1-56
Figure 1-56: Differential HSTL Class II (1.5V or 1.8V) DCI with Split-Thevenin Termination (3-state)
Z
0
IOB
0
0
1
1
IOB
DIFF_HSTL_II_DCI_T
DIFF_HSTL_II_DCI_T_18
DIFF_HSTL_II_DCI_T
DIFF_HSTL_II_DCI_T_18
DIFF_HSTL_II_DCI_T
DIFF_HSTL_II_DCI_T_18
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_T_18
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_T_18
DIFF_HSTL_II_DCI_T
DIFF_HSTL_II_DCI_T_18
V
CCO
= 1.5V for
DIFF_HSTL_II_DCI_T
V
CCO
= 1.8V for
DIFF_HSTL_II_DCI_T_18
V
CCO
= 1.5V
for DIFF_HSTL_II_DCI_T
V
CCO
= 1.8V
for DIFF_HSTL_II_DCI_T_18
R
VRN
= 2Z
0
= 100Ω
R
VRP
= 2Z
0
= 100Ω
+
–
DCI 3-stated (T pin logic High)Not 3-stated (T pin logic Low)
ug471_c1_46_021214
Z
0
R
VRN
= 2Z
0
= 100Ω
R
VRP
= 2Z
0
= 100Ω
+
–
Send Feedback

Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English