Chapter 10 10-9
Service Key Menus and Error Messages
Service Key Menus
5 DSP Wr/Rd Verifies the ability of the main processor and the DSP (digital signal processor),
both on the A9 CPU assembly, to communicate with each other through DRAM.
This also verifies that programs can be loaded to the DSP, and that most of the
main RAM access circuits operate correctly.
6 DSP RAM Verifies the A9 CPU RAM associated with the digital signal processor by using
a write/read pattern.
7 DSP ALU Verifies the A9 CPU high-speed math processing portions of the digital signal
processor.
8 DSP Intrpt Tests the ability of the A9 CPU digital signal processor to respond to interrupts
from the A10 digital IF ADC.
9 DIF Control Tests the ability of the A9 CPU main processor to write/read to the control
latches on the A10 digital IF.
10 DIF Counter Tests the ability of the A9 CPU main processor to write/read to the triple
divider on the A10 CPU. It tests the A9 CPU data buffers and A10 digital IF,
the 4 MHz clock from the A12 reference.
11 DSP Control Tests the ability of the A9 CPU digital signal processor to write to the control
latches on the A10 digital IF. Feedback is verified by the main processor. It
primarily tests the A10 digital IF, but failures may be caused by the A9 CPU.
12 Fr Pan Wr/Rd Tests the ability of the A9 CPU main processor to write/read to the front panel
processor. It tests the A2 front panel interface and processors A9 CPU data
buffering and address decoding. (See also tests 23 and 24.) This runs only when
selected.
13 GPIB Tests the ability of the A9 CPU main processor to write/read to the rear panel
control elements. It tests the A16 rear panel, and A9 CPU data buffering and
address decoding. (It does not test the GPIB interface; for that, see the
analyzer’s programmer’s guide.) This runs only when selected or with ALL
INTERNAL.
14 Post Reg Polls the status register of the A8 post-regulator, and flags these conditions:
heat sink too hot, inadequate air flow, or post-regulated supply shutdown.
15 Frac N Cont Tests the ability of the A9 CPU main processor to write/read to the control
element on the A14 fractional-N (digital) assembly. The control element must
be functioning, and the fractional-N VCO must be oscillating (although not
necessarily phase-locked) to pass.
16 Sweep Trig Tests the sweep trigger (L SWP) line from the A14 fractional-N to the A10
digital IF. The receiver with the sweep synchronizes L SWP.
17 ADC Lin It tests the linearity of the A10 digital IF ADC using the built-in ramp
generator. The test generates a histogram of the ADC linearity, where each data
point represents the relative “width” of a particular ADC code. Ideally, all codes
have the same width; different widths correspond to non-linearities.
18 ADC Ofs This runs only when selected. It tests the ability of the offset DAC, on the A10
digital IF, to apply a bias offset to the IF signals before the ADC input. This
runs only when selected.
Table 10-5 Internal Tests
Test
Number
Test Name Description
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