Chapter 7 219
Digital Signal Interface Module
Clock Timing
For Input mode, the maximum clock rate is limited by the following factors:
• sample size
• data type
• selected filter for Pre-FIR Samples
Refer to Table 7-6 for the Input mode parallel and parallel interleaved port configuration clock rates.
Clock Source
The clock signal for the N5102A module is provided in one of three ways through the following selections:
• Internal: generated internally in the interface module (requires an external reference)
• External: generated externally through the Ext Clock In connector
• Device: generated externally through the Device Interface connector
Table 7-5 Output Parallel and Parallel Interleaved Clock Rates
Logic Type Signal Type Minimum Rate Maximum Rate
LVDS IQ 1 x (clocks/sample) kHz the smaller of: 100 x (clocks /sample) MHz
or
400 MHz
IF 4 kHz 400 MHz
Other IQ 1 x (clocks/sample) kHz the smaller of: 100 x (clocks /sample) MHz
or
150 MHz
IF 4 kHz 150 MHz
Table 7-6 Input Parallel and Parallel Interleaved Clock Rates
Logic Type Data Type Minimum Rate Maximum Rate
N/A Samples 1 kHz 100 MHz
Pre-FIR Samples 1 kHz
50
1
MHz
1. The maximum sample rate depends on the selected filter when the data rate is Pre-FIR Samples. Refer to “Input Mode”
on page 232 for more information.
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