Hitachi H8/500 Series - Reset Sequence (Minimum Mode, On-Chip Memory)

ø RES Internal address bus Internal data bus (16 bits) Internal Read signal Internal Write signal
(1)
(2)
Vector
address
Vector
(4)
(3)
Instruction execution cycle
Prefetch first instruction of program
Reset vector
Internal processing cycleMinimum 6 states
(1) Instruction prefetch address (2) Operation code
(3) Program start address (4) First instruction of program
Note: This timing chart applies to the minimum mode when the program and stack areas are both in on-chip memory and the program starts at an even address.
Fig. 4-3
Figure 4-3 Reset Sequence (Minimum Mode, On-Chip Memory)
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