The timer counter can be cleared by an external reset input or by an internal compare-match signal
generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer
control register select the method of clearing.
When the timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to “1.”
The timer counter is initialized to H'00 at a reset and in the standby modes.
11.2.2 Time Constant Registers A and B (TCORA and TCORB)—H'FFD2 and H'FFD3
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually
compared with the constants written in these registers. When a match is detected, the
corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register
(TCSR).
The timer output signal (TMO) is controlled by these compare-match signals as specified by
output select bits 1 to 0 (OS1 to OS0) in the timer status/control register (TCSR).
TCORA and TCORB are initialized to H'FF at a reset and in the standby modes.
11.2.3 Timer Control Register (TCR)—H'FFD0
The TCR is an 8-bit readable/writable register that selects the clock source and the time at which
the timer counter is cleared, and enables interrupts.
The TCR is initialized to H'00 at a reset and in the standby modes.
Bit 76543210
Initial value 11111111
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 76543210
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
Initial value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
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