10.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94 and H'FF96,
H'FFA4 and H'FFA6, H'FFB4 and H'FFB6
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the corresponding output
compare flag (OCFA or OCFB) is set in the timer control/status register (TCSR).
In addition, if the output enable bit (OEA or OEB) in the timer control register (TCR) is set to “1,”
when the output compare register and FRC values match, the logic level selected by the output
level bit (OLVLA or OLVLB) in the timer control status register (TCSR) is output at the output
compare pin (FTOA or FTOB).
The FTOA and FTOB output are “0” before the first compare-match.
Because OCRA and OCRB are 16-bit registers, a temporary register (TEMP) is used when they
are written. See section 10.3, “CPU Interface” for details.
OCRA and OCRB are initialized to H'FFFF at a reset and in the standby modes.
10.2.3 Input Capture Register (ICR)—H'FF98, H'FFA8, H'FFB8
The ICR is a 16-bit read-only register.
When the rising or falling edge of the signal at the input capture input pin is detected, the current
value of the FRC is copied to the ICR. At the same time, the input capture flag (ICF) in the timer
control/status register (TCSR) is set to “1.” The input capture edge is selected by the input edge
select bit (IEDG) in the TCSR.
Because the ICR is a 16-bit register, a temporary register (TEMP) is used when the ICR is written
or read. See section 10.3, “CPU Interface” for details.
Bit 1514131211109876543210
Initial value 1111111111111111
Read/WriteR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 1514131211109876543210
Initial value 0000000000000000
Read/Write RRRRRRRRRRRRRRRR
182
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