Hitachi H8/500 Series - Reset During Memory Access (Mode 2)

Masked-ROM Versions
A to A70
RES
P1 / ø*
0
Internal reset signal
R/W
AS, RD and DS (read)
WR and DS (write)
D to D (write)70
I/O ports
High impedance
High impedance
H’00
External memory access
T
1 T2 T3
P5 /A to P5 /A715 08
High impedance
*
The dotted line indicates that P10/ø is an input port if the corresponding DDR bit is 0,
but a clock output pin if the DDR bit is 1.
Figure E-4 Reset during Memory Access (Mode 2)
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