14.2.8 Bit Rate Register (BRR)—H'FFD9
The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines
the bit rate output by the baud rate generator.
The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes.
Tables 14-3 and 14-4 show examples of BRR (N) and CKS (n) settings for commonly used bit
rates.
Table 14-3 Examples of BRR Settings in Asynchronous Mode (1)
XTAL Frequency (MHz)
2 2.4576 4 4.194304
Bit Error Error Error Error
Rate n N (%) n N (%) n N (%) n N (%)
110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 –0.04
150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21
300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21
600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21
1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 –0.70
2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14
4800 — — — 0 7 0 0 12 +0.16 0 13 –2.48
9600 — — — 0 3 0 — — — — — —
19200 — — — 0 1 0 — — — — — —
31250 — — — — — — 0 1 0 — — —
38400 — — — 0 0 0 — — — — — —
Bit 76543210
Initial value 11111111
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
255
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