Hitachi H8/500 Series - Setting of Output Compare Flags; Timing of Output Compare

Output Timing: When a compare-match occurs, the logic level selected by the output level bit
(OLVLA or OLVLB) in the TCSR is output at the output compare pin (FTOA or FTOB).
Figure 10-5 shows the timing of this operation for compare-match A.
N
N
N + 1
Ø
FRC
OCR
Internal compare-
match signal
OCF
ø
ø
FTOA
Internal compare-
match A signal
OLYLA
Figure 10-4 Setting of Output Compare Flags
Figure 10-5 Timing of Output Compare A
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