Hitachi H8/500 Series - Pin States During On-Chip Memory Access; Pin States During Access to On-Chip Memory

3.7.3 Pin States during On-Chip Memory Access
T state1 T state2
ø
A to A
R/W (write access)
19 0
AS, DS, RD, WR
D to D 70
R/W (read access)
“High”
High-impedance
Figure 3-7 Pin States during Access to On-Chip Memory
65
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