Hitachi H8/500 Series - Reset During Memory Access (Mode 4)

Masked-ROM Versions
A to A70
RES
P1 / ø*0
Internal reset signal
R/W
AS, RD and DS (read)
WR and DS (write)
D to D (write)70
I/O ports
High impedance
H’00
T
1 T2 T3 T1
High impedance
High impedance
P6 /A to P6 /A ,
P5 /A to P5 /A
319 016
715 08
*
The dotted line indicates that P10/ø is an input port if the corresponding DDR bit is 0,
but a clock output pin if the DDR bit is 1.
Figure E-8 Reset during Memory Access (Mode 4)
445
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