Hitachi H8/500 Series - Reset During Memory Access (Mode 7)

Masked-ROM Versions
RES
P1 / ø*
0
Internal reset signal
I/O ports
High impedance
P1 /E*
0
*
The dotted line indicates that P10/ø and P10/E are input port if the corresponding DDR
bit is 0, but clock output pins if the DDR bit is 1.
Figure E-10 Reset during Memory Access (Mode 7)
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