Hitachi H8/500 Series - Data Transfer Enable Registers

Starting of the DTC is controlled by the four data transfer enable registers, which are located in
high addresses in page 0. Table 6-2 lists these registers.
Table 6-2 Data Transfer Enable Registers
Name Abbreviation Read/Write Address Initial Value
Data transfer A DTEA R/W H'FFF4 H'00
enable B DTEB R/W H'FFF5 H'00
register C DTEC R/W H'FFF6 H'00
D DTED R/W H'FFF7 H'00
6.2 Register Descriptions
6.2.1 Data Transfer Mode Register (DTMR)
The data transfer mode register is a 16-bit register, the first three bits of which designate the data
size and specify whether to increment the source and destination addresses.
Bit 15—Sz (Size): This bit designates the size of the data transferred.
Bit 15
Sz Description
0 Byte transfer
1 Word transfer* (two bytes at a time)
* For word transfer, the source and destination addresses must be even addresses.
Bit 14—SI (Source Increment): This bit specifies whether to increment to source address.
Bit 14
SI Description
0 Source address is not incremented.
1 1) If Sz = 0: Source address is incremented by +1 after each data transfer.
2) If Sz = 1: Source address is incremented by +2 after each data transfer.
Bit 1514131211109876543210
SzSIDI—————————————
Read/Write ————————————————
115
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