Hitachi H8/500 Series - Bus-Right Release Cycle (During Internal CPU Operation)

RD, WR
R/W, DS
D –D
70
A –A19 0
ø
BREQ
BACK
Bus-right release cycle CPU cycleExternal access cycle
Ti Ti Ti TX TX T1** TXTi
Fig. 3-15
(1) (2) (3) (4)
(1) The BREQ pin is sampled at the start of a TI state and the Low level is detected.
(2) At the end of the internal operation cycle, the BACK pin goes Low and the CPU releases the bus.
(3) The BREQ pin is sampled at the T
X state and a High level is detected.
(4) The BACK pin is returned to the High level, ending the bus-right release cycle.
* T
I : Internal CPU operation state.
T
X : Bus-right released state.
Figure 3-15 Bus-Right Release Cycle (During Internal CPU Operation)
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