Hitachi H8/500 Series - Appendix A Instructions; Instruction Set

Appendix A Instructions
A.1 Instruction Set
Operation Notation
Rd General register (destination operand) FP Frame pointer
Rs General register (source operand) #IMM Immediate data
Rn General register disp Displacement
(EAd) Destination operand + Add
(EAs) Source operand – Subtract
CCR Condition code register × Multiply
N N (Negative) flag in CCR ÷ Divide
Z Z (Zero) flag in CCR ∧ Logical AND
V V (Overflow) flag in CCR ∨ Logical OR
C C (Carry) flag in CCR ⊕ Logical exclusive OR
CR Control register → Move
PC Program counter ↔ Swap
CP Code page register ¬ Logical NOT
SP Stack pointer
Condition Code Notation
↕ Changed after instruction execution
0 Cleared to 0
1 Set to 1
— Value before operation is retained
∆ Changed depending on condition
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