Hitachi H8/500 Series - Stack Status after Interrupt Handling Sequence

5.4.2 Stack Status after Interrupt Handling Sequence
Figure 5-3 (a) and (b) show the stack before and after the interrupt exception-handling sequence.
SP
Address
SP
2m – 4
2m – 3
2m – 2
2m – 1
2m
Address
2m – 4
2m – 3
2m – 2
2m – 1
2m
Upper 8 bits of SR
Lower 8 bits of SR
Upper 8 bits of PC
Lower 8 bits of PC
(After)(Before)
Stack area
Save to stack
Notes:
1. PC: The address of the next instruction to be executed is saved.
2. Register saving and restoring must start at an even address (e.g 2m).
Figure 5-3 (a) Stack before and after Interrupt Exception-Handling
(Minimum Mode)
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