Hitachi H8/500 Series - Package Dimensions

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Figure G-3 Package Dimensions (FP-80A)

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Table of Contents3
Section 1 Overview22
Features22
Addressing Modes23
Block Diagram25
Pin Arrangements and Functions26
Pin Arrangement26
Pin Arrangement (CP-84, Top View)26
Section 2 MCU Operating Modes and Address Space43
Overview43
Operating Modes43
Mode Descriptions44
Address Space Map45
Page Segmentation45
Address Space in each Mode46
Address Allocations47
Mode Control Register (MDCR)49
Mode Control Register49
Section 3 CPU50
Overview50
Features50
Address Space51
CPU Operating Modes51
Register Configuration52
Registers in the CPU52
CPU Register Descriptions53
General Registers53
Stack Pointer53
Control Registers54
Interrupt Mask Levels55
Interrupt Mask Bits after an Interrupt Is Accepted55
Combinations of Page Registers with Other Registers57
Short Absolute Addressing Mode and Base Register58
Initial Register Values59
Data Formats60
Data Formats in General Registers60
Initial Values of Registers60
Data Formats in Memory61
General Register Data Formats61
Data Formats in Memory62
Instructions63
Basic Instruction Formats63
Data Formats on the Stack63
Addressing Modes64
Effective Address Calculation66
Instruction Set69
Overview69
Instruction Classification69
Data Transfer Instructions71
Arithmetic Instructions72
Logic Operations73
Logic Operation Instructions73
Shift Operations74
Shift Instructions74
Bit Manipulations75
Bit-Manipulation Instructions75
Branching Instructions76
System Control Instructions78
Operating Modes81
Minimum Mode81
Short-Format Instructions and Equivalent General Formats81
Maximum Mode82
Basic Operational Timing82
Overview82
On-Chip Memory Access Cycle83
On-Chip Memory Access Timing83
Pin States During On-Chip Memory Access84
Pin States During Access to On-Chip Memory84
Register Field Access Cycle (Addresses H'FF80 to H'FFFF)85
Register Field Access Timing85
Pin States During Register Field Access (Addresses H'FF80 to H'FFFF)86
Pin States During Register Field Access86
External Access Cycle87
CPU States88
Overview88
Operating States89
Power-Down State89
Program Execution State90
Exception-Handling State90
State Transitions90
Bus-Released State91
Bus-Right Release Cycle (During On-Chip Memory Access Cycle)92
Bus-Right Release Cycle (During External Access Cycle)93
Bus-Right Release Cycle (During Internal CPU Operation)94
Reset State96
Power-Down State96
Programming Notes97
Restriction on Address Location97
Note on MULXU Instruction98
Section 4 Exception Handling100
Overview100
Types of Exception Handling and Their Priority100
Hardware Exception-Handling Sequence101
Exception Factors and Vector Table101
Types of Factors Causing Exception Handling102
Exception Vector Table103
Reset104
Overview104
Reset Sequence104
Stack Pointer Initialization105
Reset Vector105
Reset Sequence (Minimum Mode, On-Chip Memory)106
Reset Sequence (Maximum Mode, External Memory)107
Address Error108
Illegal Instruction Prefetch108
Word Data Access at Odd Address108
Off-Chip Address Access in Single-Chip Mode108
Trace109
Interrupts109
Interrupt Sources (and Number of Interrupt Types)110
Invalid Instruction111
Trap Instructions and Zero Divide111
Cases in Which Exception Handling Is Deferred111
Instructions that Disable Interrupts111
Disabling of Exceptions Immediately after a Reset112
Disabling of Interrupts after a Data Transfer Cycle112
Stack Status after Completion of Exception Handling113
Stack after Exception Handling Sequence113
PC Value Pushed on Stack for Trace115
Interrupts, Trap Instructions, and Zero Divide Exceptions115
Instruction Exceptions115
Notes on Use of the Stack115
Section 5 Interrupt Controller116
Overview116
Features116
Block Diagram117
Interrupt Controller Block Diagram117
Register Configuration118
Interrupt Types118
External Interrupts118
Interrupt Controller Registers118
Internal Interrupts120
Interrupt Vector Table120
Interrupts, Vectors, and Priorities121
Register Descriptions122
Interrupt Priority Registers a to D (IPRA to IPRD)122
Assignment of Interrupt Priority Registers122
Timing of Priority Setting123
Interrupt Handling Sequence123
Interrupt Handling Flow123
Interrupt Handling Flowchart125
Stack Status after Interrupt Handling Sequence126
Timing of Interrupt Exception-Handling Sequence127
Interrupts During Operation of the Data Transfer Controller127
Interrupt Sequence (Minimum Mode, On-Chip Memory)128
Interrupt Sequence (Maximum Mode, External Memory)129
Interrupt Response Time130
Number of States before Interrupt Service130
Section 6 Data Transfer Controller131
Overview131
Features131
Block Diagram131
Register Configuration132
Data Transfer Mode Register (DTMR)132
Block Diagram of Data Transfer Controller132
Internal Control Registers of the DTC132
Data Transfer Enable Registers133
Data Transfer Source Address Register (DTSR)134
Data Transfer Destination Register (DTDR)134
Data Transfer Count Register (DTCR)134
Data Transfer Enable Registers a to D (DTEA to DTED)135
Assignment of Data Transfer Enable Registers135
Data Transfer Operation136
Data Transfer Cycle136
Flowchart of Data Transfer Cycle137
DTC Vector Table138
DTC Vector Table Entry139
Addresses of DTC Vectors139
Location of Register Information in Memory140
Length of Data Transfer Cycle140
Order of Register Information140
Number of States Per Data Transfer141
Procedure for Using the DTC142
Number of States before Interrupt Service142
Example143
DTC Control Register Information Set in RAM143
Use of DTC to Receive Data Via Serial Communication Interface144
Section 7 Wait-State Controller145
Overview145
Features145
Block Diagram146
Register Configuration146
Block Diagram of Wait-State Controller146
Wait-State Control Register147
Operation in each Wait Mode148
Programmable Wait Mode148
Wait Modes148
Pin Wait Mode149
Programmable Wait Mode149
Pin Wait Mode150
Pin Auto-Wait Mode151
Section 8 Clock Pulse Generator152
Overview152
Block Diagram152
Oscillator Circuit152
Block Diagram of Clock Pulse Generator152
Connection of Crystal Oscillator (Example)153
Crystal Oscillator Equivalent Circuit153
External Crystal Parameters153
Notes on Board Design Around External Crystal154
External Clock Input (Example)154
System Clock Divider155
Phase Relationship of Ø Clock and E Clock155
Section 9 I/O Ports156
Overview156
Input/Output Port Summary157
Port 1159
Overview159
Port 1 Registers159
Pin Functions159
And P1160
Pin Functions in each Mode162
Port 1 Pin Functions in Expanded Modes162
Port 1 Pin Functions in Single-Chip Modes164
Port 2166
Port 2 Registers166
Pin Functions in each Mode167
Port 2 Pin Functions in Expanded Modes167
Port 3168
Overview168
Port 2 Pin Functions in Single-Chip Mode168
Port 3 Registers169
Pin Functions in each Mode170
Port 3 Pin Functions in Expanded Modes170
Port 3 Pin Functions in Single-Chip Mode171
Port 4172
Port 4 Registers172
Pin Functions in each Mode173
Port 4 Pin Functions in Expanded Modes173
Overview174
Port 4 Pin Functions in Single-Chip Mode174
Port 5 Registers175
Pin Functions in each Mode176
Port 5 Pin Functions in Single-Chip Mode177
Built-In MOS Pull178
Overview180
Port 6 Registers181
Port 7184
Overview184
Port 7 Registers185
Pin Functions186
Port 7 Pin Functions187
Port 8189
Overview189
Port 8 Registers189
Port 9190
Overview190
Port 9 Registers190
Port 9 Pin Functions192
Pin Functions193
Section 10 16-Bit Free-Running Timers194
Overview194
Features194
Block Diagram195
Block Diagram of 16-Bit Free-Running Timer195
Input and Output Pins196
Input and Output Pins of Free-Running Timer Module196
Register Configuration197
Register Descriptions198
Free-Running Counter (FRC)-H'FF92, H'FFA2, H'FFB2198
Input Capture Register (ICR)-H'FF98, H'FFA8, H'FFB8199
Timer Control Register (TCR)200
Timer Control/Status Register (TCSR)202
CPU Interface205
Operation207
FRC Incrementation Timing207
Output Compare Timing208
Increment Timing for External Clock Input208
Setting of Output Compare Flags209
Timing of Output Compare209
Input Capture Timing210
Clearing of FRC by Compare-Match210
Input Capture Timing (Usual Case)210
Input Capture Timing (1-State Delay)211
Setting of Input Capture Flag211
Setting of FRC Overflow Flag (OVF)212
CPU Interrupts and DTC Interrupts212
Setting of Overflow Flag (OVF)212
Free-Running Timer Interrupts212
Synchronization of Free-Running Timers 1213
Synchronization after a Reset213
Synchronization by Writing to Frcs213
Sample Application217
Application Notes217
Contention between OCR Write and Compare-Match220
Effect of Changing Internal Clock Sources221
Effect of Changing Internal Clock Sources222
Section 11 8-Bit Timer223
Overview223
Features223
Block Diagram224
Block Diagram of 8-Bit Timer224
Input and Output Pins225
Register Configuration225
Register Descriptions225
Timer Counter (TCNT)-H'FFD4225
Input and Output Pins of 8-Bit Timer225
Time Constant Registers a and B226
Timer Control Register (TCR)-H'FFD0226
Timer Control/Status Register (TCSR)228
Operation230
TCNT Incrementation Timing230
Compare Match Timing231
Count Timing for External Clock Input231
Setting of Compare-Match Flags232
Timing of Timer Output232
External Reset of TCNT233
Timing of Compare-Match Clear233
Timing of External Reset233
Setting of TCNT Overflow Flag234
CPU Interrupts and DTC Interrupts234
Setting of Overflow Flag (OVF)234
Sample Application235
Example of Pulse Output235
Application Notes236
TCNT Write-Clear Contention236
TCNT Write-Increment Contention237
Contention between TCOR Write and Compare-Match238
Priority Order of Timer Output239
Section 12 PWM Timer242
Overview242
Features242
Block Diagram242
Input and Output Pins243
Block Diagram of PWM Timer243
Output Pins of PWM Timer Module243
Register Configuration244
Register Descriptions244
Timer Counter (TCNT)-H'FFC2, H'FFC4, H'FFCA244
PWM Timer Registers244
Duty Register (DTR)-H'FFC1, H'FFC5, H'FFC9245
Timer Control Register (TCR)-H'FFC0, H'FFC4, H'FFC8245
Operation247
PWM Timer Parameters for 10Mhz System Clock247
PWM Timing248
Application Notes249
Section 13 Watchdog Timer250
Overview250
Features250
Block Diagram251
Register Configuration251
Block Diagram of Timer Counter251
Register Descriptions252
Timer Counter TCNT-H'FFED252
Timer Control/Status Register (TCSR)-H'FFEC (Read), H'FFED (Write)252
Notes on Register Access254
Writing to TCNT and TCSR254
Operation255
Watchdog Timer Mode255
Read Addresses of TCNT and TCSR255
Interval Timer Mode256
Operation in Watchdog Timer Mode256
Operation in Software Standby Mode257
Operation in Interval Timer Mode257
Setting of Overflow Flag258
Application Notes258
Setting of OVF Bit258
TCNT Write-Increment Contention259
Section 14 Serial Communication Interface260
Overview260
Features260
Block Diagram261
Block Diagram of Serial Communication Interface261
Input and Output Pins262
Register Configuration262
Register Descriptions262
Receive Shift Register (RSR)262
SCI Input/Output Pins262
SCI Registers262
Receive Data Register (RDR)-H'FFDD263
Transmit Shift Register (TSR)263
Transmit Data Register (TDR)-H'FFDB263
Serial Mode Register (SMR)-H'FFD8264
Serial Control Register (SCR)-H'FFDA266
Serial Status Register (SSR)-H'FFDC268
Bit Rate Register (BRR)-H'FFD9270
Examples of BRR Settings in Synchronous Mode273
Operation274
Overview274
Communication Formats Used by SCI274
SCI Clock Source Selection274
Asynchronous Mode275
Data Format in Asynchronous Mode275
Phase Relationship between Clock Output and Transmit Data276
Data Formats in Asynchronous Mode276
Synchronous Mode279
Receive Errors279
Data Format in Synchronous Mode280
CPU Interrupts and DTC Interrupts283
Application Notes284
SCI Interrupts284
SSR Bit States and Data Transfer When Multiple Receive Errors Occur285
Sampling Timing (Asynchronous Mode)286
Section 15 A/D Converter287
Overview287
Features287
Block Diagram288
Block Diagram of A/D Converter288
Input Pins289
Register Configuration289
A/D Input Pins289
A/D Registers289
Assignment of Data Registers to Analog Input Channels290
A/D Control/Status Register (ADCSR)-H'FFE8291
CPU Interface293
Operation294
Read Access to A/D Data Register (When Register Contains H'AA40)294
Single Mode295
A/D Operation in Single Mode (When Channel 1 Is Selected)297
Scan Mode298
A/D Operation in Scan Mode (When Channels 0 to 2 Are Selected)300
Input Sampling Time and A/D Conversion Time301
A/D Conversion Timing302
A/D Conversion Time (Single Mode)302
Interrupts and the Data Transfer Controller303
Section 16 RAM304
Overview304
Block Diagram304
Block Diagram of On-Chip RAM304
Register Configuration305
RAM Control Register (RAMCR)305
Operation305
Expanded Modes (Modes 1, 2, 3, and 4)305
RAM Control Register305
Single-Chip Mode (Mode 7)306
Section 17 ROM307
Overview307
Block Diagram307
ROM Usage in each MCU Mode307
PROM Modes308
PROM Mode Setup308
Block Diagram of On-Chip ROM308
Selection of PROM Mode308
Socket Adapter Pin Arrangements and Memory Map309
Socket Adapter309
Socket Adapter Pin Arrangements310
Programming311
Writing and Verifying311
Memory Map in PROM Mode311
Selection of Sub-Modes in PROM Mode311
High-Speed Programming Flowchart312
CC = 6.0V ±0.25V, V Pp = 12.5V ±0.3V, V Ss = 0V313
AC Characteristics (When VCC = 6.0V ±0.25V, VPP = 12.5V ±0.3V313
Notes on Writing314
PROM Write/Verify Timing314
Reliability of Written Data315
Recommended Screening Procedure315
Erasing of Data316
Handling of Windowed Packages316
Erasing Conditions316
Socket for 84-Pin LCC Package317
Section 18 Power-Down State318
Overview318
Sleep Mode319
Transition to Sleep Mode319
Exit from Sleep Mode319
Software Standby Mode319
Transition to Software Standby Mode319
Software Standby Control Register (SBYCR)320
Software Standby Control Register320
Exit from Software Standby Mode321
Sample Application of Software Standby Mode321
Application Notes322
NMI Timing of Software Standby Mode (Application Example)322
Hardware Standby Mode323
Recovery from Hardware Standby Mode323
Timing Sequence of Hardware Standby Mode324
Hardware Standby Sequence324
Section 19 E Clock Interface325
Overview325
Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes326
Execution Cycle of Instruction Synchronized with E Clock in Expanded Modes327
Section 20 Electrical Specifications328
Electrical Characteristics328
DC Characteristics328
Absolute Maximum Ratings328
DC Characteristics329
Allowable Output Current Sink Values330
AC Characteristics331
Example of Circuit for Driving a Darlington Transistor Pair331
Example of Circuit for Driving an LED331
Bus Timing331
Control Signal Timing333
Output Load Circuit334
Timing Conditions of On-Chip Supporting Modules334
A/D Converter Characteristics335
MCU Operatinal Timing335
Bus Timing335
Control Signal Timing335
Basic Bus Cycle (Without Wait States) in Expanded Modes336
Basic Bus Cycle (with 1 Wait State) in Expanded Modes337
Bus Cycle Synchronized with E Clock338
Reset Input Timing339
Interrupt Input Timing339
NMI Pulse Width (for Recovery from Software Standby Mode)339
Clock Timing340
Bus Release State Timing340
E Clock Timing340
Clock Oscillator Stabilization Timing341
I/O Port Timing342
16-Bit Free-Running Timer Timing343
Free-Running Timer Input/Output Timing343
External Clock Input Timing for Free-Running Timers343
8-Bit Timer Timing344
Pulse Width Modulation Timer Timing345
Serial Communication Interface Timing345
PWM Timer Output Timing345
SCI Input/Output Timing (Synchronous Mode)345
Appendix A Instructions346
Instruction Set346
Instruction Codes351
Operation Code Map360
Instruction Execution Cycles367
Calculation of Instruction Execution States367
Tables of Instruction Execution Cycles368
Appendix B Register Field376
Register Addresses and Bit Names376
Register Descriptions381
A) Schematic Diagram of Port 1, Pin P1416
B) Schematic Diagram of Port 1, Pin P1416
C) Schematic Diagram of Port 1, Pin P1417
D) Schematic Diagram of Port 1, Pin P1418
E) Schematic Diagram of Port 1, Pin P1419
Port 2 Port Read422
Port 3 Port Read423
Port 4 Port Read424
Port 5 Port Read425
Port 6 Port Read426
And P9433
And P9434
C) Schematic Diagram of Port 9, Pin P9435
D) Schematic Diagram of Port 9, Pin P9436
E) Schematic Diagram of Port 9, Pin P9437
Reset During Memory Access (Mode 1)444
Reset During Memory Access (Mode 1)445
Reset During Memory Access (Mode 2)447
Reset During Memory Access (Mode 2)448
Reset During Memory Access (Mode 3)450
Reset During Memory Access (Mode 3)451
Reset During Memory Access (Mode 4)453
Reset During Memory Access (Mode 4)454
Reset During Memory Access (Mode 7)455
Reset During Memory Access (Mode 7)456
Package Dimensions458
Package Dimensions459

Hitachi H8/500 Series - Package Dimensions

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