Hitachi H8/500 Series - Single-Chip Mode (Mode 7)

16.3.2 Single-Chip Mode (Mode 7)
If the RAME bit is set to 1, accesses to addresses H'FB80 to H'FF7F are directed to the on-chip
RAM. If the RAME bit is cleared to 0, access of any type (instruction fetch or data read or write)
to addresses H'FB80 to H'FF7F causes an address error and initiates the CPU’s exception-handling
sequence.
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