Hitachi H8/500 Series - Data Transfer Source Address Register (DTSR); Data Transfer Destination Register (DTDR); Data Transfer Count Register (DTCR)

Bit 13—DI (Destination Increment): This bit specifies whether to increment to destination
address.
Bit 13
DI Description
0 Destination address is not incremented.
1 1) If Sz = 0: Destination address is incremented by +1 after each data transfer.
2) If Sz = 1: Destination address is incremented by +2 after each data transfer.
Bits 12 to 0—Reserved Bits: These bits are reserved.
6.2.2 Data Transfer Source Address Register (DTSR)
The data transfer source register is a 16-bit register that designates the data transfer source
address. For word transfer this must be an even address. In the maximum mode, this address is
implicitly located in page 0.
6.2.3 Data Transfer Destination Register (DTDR)
The data transfer destination register is a 16-bit register that designates the data transfer
destination address. For word transfer this must be an even address. In the maximum mode, this
address is implicitly located in page 0.
6.2.4 Data Transfer Count Register (DTCR)
Bit 1514131211109876543210
Read/Write ————————————————
Bit 1514131211109876543210
Read/Write ————————————————
Bit 1514131211109876543210
Read/Write ————————————————
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