Contention between TCNT Write and Increment: If a timer counter increment pulse is
generated during the T3 state of a write cycle to the timer counter, the write takes priority and the
timer counter is not incremented.
Figure 11-10 shows this type of contention.
TCNT address
NM
Write data
Internal Address
bus
Internal write
signal
ø
TCNT clock
pulse
TCNT
Write cycle: CPU writes to TCNT
T
1 T2 T3
Figure 11-10 TCNT Write-Increment Contention
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