Port 5 Data Register (P5DR)—H'FF8A
P5DR is an 8-bit register containing the data for pins P57 to P50.
At a reset and in the hardware standby mode, P5DR is initialized to H'00.
When the CPU reads P5DR, for output pins it reads the value in the P5DR latch, but for input
pins, it obtains the pin status directly.
9.6.3 Pin Functions in Each Mode
Port 5 operates in one way in modes 1 and 3, in another way in modes 2 and 4, and in a third way
in mode 7. Separate descriptions are given below.
Pin Functions in Modes 1 and 3: In modes 1 and 3 (expanded modes in which the on-chip ROM
is not used), all bits of P5DDR are automatically set to “1” for output, and the pins of port 5 carry
bits A15 – A8 of the address bus. Figure 9-12 shows the pin functions for modes 1 and 3.
Bit 76543210
P5
7 P56 P55 P54 P53 P52 P51 P50
Initial value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
A15 (output)
A
14 (output)
A
13 (output)
Port A
12 (output)
5A
11 (output)
A
10 (output)
A
9 (output)
A
8 (output)
Figure 9-12 Port 5 Pin Functions in Modes 1 and 3
159
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