The PWM timer counters are initialized to H'00 at a reset and in the standby modes, and when the
OE bit is cleared to 0.
12.2.2 Duty Register (DTR)—H'FFC1, H'FFC5, H'FFC9
The duty registers (DTR) specify the duty factor of the output pulse. Any duty factor from 0 to
100% can be selected, with a resolution of 1/250. Writing 0 (H'00) in a DTR gives a 0% duty
factor; writing 125 (H'7D) gives a 50% duty factor; writing 250 (H'FA) gives a 100% duty factor.
The timer count is continually compared with the DTR contents. If the DTR value is not 0, when
the count increments from H'00 to H'01 the PWM output signal is set to 1. When the count
increments to the DTR value, the PWM output returns to 0. If the DTR value is 0 (duty factor
0%), the PWM output remains constant at 0.
The DTRs are double-buffered. A new value written in a DTR while the timer counter is running
does not become valid until after the count changes from H'F9 to H'00. When the timer counter is
stopped (while the OE bit is 0), new values become valid as soon as written. When a DTR is
read, the value read is the currently valid value.
The DTRs are initialized to H'FF at a reset and in the standby modes.
12.2.3 Timer Control Register (TCR)—H'FFC0, H'FFC4, H'FFC8
The TCRs are 8-bit readable/writable registers that select the clock source and control the PWM
outputs.
The TCRs are initialized to H'38 at a reset and in the standby modes.
Bit 76543210
Initial value 11111111
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 76543210
OE OS — — — CKS2 CKS1 CKS0
Initial value 00111000
Read/Write R/W R/W — — — R/W R/W R/W
230
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