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Hitachi H8/500 Series - Page 246

Hitachi H8/500 Series
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Bit 7—Output Enable (OE): This bit enables the timer counter and the PWM output.
Bit 7
OE Description
0 PWM output is disabled. TCNT is cleared to H'00 and stopped. (Initial value)
1 PWM output is enabled. TCNT runs.
Bit 6—Output Select (OS): This bit selects positive or negative logic for the PWM output.
Bit 6
OS Description
0 Positive logic; positive-going PWM pulse, 1 = High (Initial value)
1 Negative logic; negative-going PWM pulse, 1 = Low
Bits 5 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight clock
sources obtained by dividing the system clock (ø).
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0 Description
0 0 0 ø/2 (Initial value)
001 ø/8
0 1 0 ø/32
0 1 1 ø/128
1 0 0 ø/256
1 0 1 ø/1024
1 1 0 ø/2048
1 1 1 ø/4096
From the clock source frequency, the resolution, period, and frequency of the PWM output can be
calculated as follows.
Resolution = 1/clock source frequency
PWM period = resolution × 250
PWM frequency = 1/PWM period
If the ø clock frequency is 10MHz, then the resolution, period, and frequency of the PWM output
for each clock source are given in table12-3.
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